Integrated circuit (IC) design can include conversion of a circuit description into a specification of interconnected transistors and other circuit elements laid out on an IC. The design often utilizes techniques such as circuit level simulation, placement and routing of circuit elements, and/or application of design for manufacturing considerations. Simulation can also be used to assess whether the design can achieve performance and timing metrics that are desired for the IC.
Different approaches can be taken to achieving the performance metrics for a manufactured part. In some examples, static performance analysis can be used to determine the performance metrics.
One approach to static analysis uses a worst-case approach, for example, characterizing signal propagation delay through a particular type of logic gate according to a minimum and maximum propagation time. Compound effects, such as propagation delay though a path of gates makes use of the individual worst-case characterizations to derive an overall worst-case path delay. Such an approach may be acceptable when a range of delays through a gate is relatively small compared to typical values and a design based on such an approach may achieve close to optimum performance. However, when the range of variation is relatively large, then a worst-case analysis approach often yields a significantly conservative design.
Static analysis approaches can also use statistical distributions rather than worst-case analysis. For example, as shown in FIG. 1, the delay through a gate can be characterized by a statistical distribution 10. The statistical distribution includes a mean delay 12 (e.g., the mean rise time or fall time) and a variation of the delay 14 (e.g., a variation in the rise time or fall time). As shown in FIG. 2, in statistical timing analysis, the compound effect of a path delay through a series of gates (e.g., gates 32, 34, and 36) is computed from the distribution for each of the gates 32, 34, and 36 (e.g., distributions 42, 44, and 46). The total delay for a path through a series of gates can be represented as a distribution based on the statistical distributions for each of the gates.
Static analysis, either worst case or statistically based, uses characterizations of circuit elements such as logic gates that are typically provided by a semiconductor manufacturer to match the fabrication process to be used. For example, the manufacturer of a chip may determine a particular set of parameters that characterize the fabrication process by making electrical and/or optical measurements of test chips. One way of characterizing the transition speed of a gate involves using a ring oscillator composed of such gates on a test chip. Propagation speed through the gate can be determined from the oscillation frequency of the ring oscillator. The manufacturer provides parameters that characterize performance of various circuit elements to the designer of the integrated circuit to enable static analysis of the integrated circuit prior to fabrication.